1. Field of the Invention
The present invention relates to an apparatus for and a method of detecting a delay fault in a phase-locked loop circuit, and more particularly, relates to a delay fault detecting apparatus and a delay fault detecting method which are suitable for detecting delay faults in phase-locked loop (hereinafter referred to as PLL) circuits formed on VLSI (very large scale integrated circuit) chips respectively.
2. Description of the Related Art
A synchronous system performs a cooperative operation by sharing a timing of a clock edge with one another. The more the timing of the shared edge is controlled at high accuracy, the more the synchronous system can operate at a high rate. FIG. 1 shows an example of the synchronous system. This system has such a configuration that a plurality of (in this example, two) VLSI chips 11 and 12 are placed on a single board (not shown). A reference clock .phi. is supplied to each of the VLSI chips 11 and 12 from a high precision oscillator (for example, a crystal-based clock generator) 13 provided on the board. PLL circuits 14 and 15 on those VLSI chips output, as shown in FIG. 2, clocks .phi..sub.11, .phi..sub.12, and .phi..sub.21, .phi..sub.22 generated by the on-chip clock generators with their edges synchronized with the edge of the reference clock .phi. supplied from the outside, and those clocks are distributed to subsystems 16 and 17, respectively. (For example, refer to a reference literature d1.)
As stated above, by synchronizing the edge of an internal clock with respect to the edge of a reference clock, data can be transmitted and received between different chips. The PLL circuits 14 and 15 play a role in minimizing a clock skew and ensuring a high speed operation of the system, by aligning the frequency and the phase of an oscillation waveform of a voltage-controlled oscillator (hereinafter referred to as VCO) with respect to the frequency and the phase of the inputted reference clock .phi..
As is well known, in a microcomputer, an instantaneous value (a peak-to-peak jitter or the like) of the worst case may determine the operational frequency of the microcomputer. Therefore, it is necessary in the microcomputer to positively detect, by a test, any fault that increases a clock skew even for an instant.
Next, an influence of a delay fault in a PLL circuit on a system will be discussed. FIG. 3 shows an example of the PLL circuit. This PLL circuit comprises a phase-frequency detector 21, a charge pump circuit 22, a loop filter 23, a VCO 24, and a clock decode and buffer circuit 25. Now, it is assumed that a delay fault DF1 is present at the reference clock input side of the phase-frequency detector 21. As shown in FIG. 4, a reference clock .phi..sub.REF (indicated by a solid line) applied to the phase-frequency detector 21 of the PLL circuit becomes a clock .phi. (indicated by a dotted line) which has been delayed by a constant time interval due to the delay fault DF1 present at the input side, and the delayed clock .phi. is fed into the charge pump circuit 22 at the next stage. In the PLL circuit, an edge of an internal clock .phi..sub.1 (indicated by a solid line) outputted from the clock decode and buffer circuit 25 is synchronized with respect to the edge of the dotted line clock .phi. which has been delayed by the constant time interval. As a result, a clock skew occurs in response to the delay fault DF1. Moreover, the clock skew, which is a deviation generated at the reference clock input side, is not compensated in the PLL circuit and remains as a constant value. As a result, it appears that a large steady-state deviation remains.
Since this delay fault DF1 is not a fault of an internal block (internal component) of the PLL circuit, the PLL circuit gets into a synchronous state. Accordingly, it is difficult to detect a delay fault at the reference clock input side even if internal blocks of the PLL circuit are tested. However, a delay fault of this type can easily be detected by comparing the external reference clock .phi..sub.REF with the internal clock .phi..sub.1.
Next, as shown in FIG. 5, it is assumed that a delay fault DF2 is present at the Up signal input side of the charge pump circuit 22. Due to the delay fault DF2, a timing in the charge pump circuit 22 for converting an Up signal inputted thereto from the phase-frequency detector 21 to an analog signal to output the analog signal is delayed. Further, the delay of the analog signal causes a timing of an oscillation waveform of the VCO 24 to delay.
In the next step, the phase-frequency detector 21 compares the edge of the reference clock .phi..sub.REF with the edge of the internal clock .phi..sub.1, and controls the timing of the oscillation waveform of the VCO 24 by using, as a phase error signal, a time interval between the rising edges of the two clocks. The control for the feedback loop is carried out until the rising edges of both the clocks are aligned with each other. Therefore, the delay fault DF2 appears simultaneously with a state transition and is compensated by the feedback. The delay time has its maximum value when the state transition occurs. Consequently, as shown in FIG. 6, a clock slew has also its maximum value when the state transition occurs, and it is decreased to zero with the lapse of time. In this manner, since a PLL circuit is a feedback system, a transient skew occurs. A timing at which a transient skew occurs is limited, and hence it is difficult to detect the transient skew by a test.
As mentioned above, in the case that a delay fault DF1 is present at the reference clock input end of the phase-frequency detector 21, a clock skew having a constant time interval occurs. This clock skew is not compensated in the PLL circuit. On the other hand, in the case that a delay fault DF2 is present at the Up signal input end of the charge pump circuit 22, a large clock skew transiently appears in correspondence to a state transition shown in FIG. 7. This transient clock skew DF2 is compensated in the PLL circuit and approaches toward zero. All the delay faults of other blocks (an input end of the loop filter 23 and an input end of the VCO 24) of the PLL circuit can be mapped to the delay fault in the input end of the charge pump circuit 22.
A stuck-at fault testing (for example, refer to a reference literature d2) has conventionally been utilized most widely in the verification test and the manufacturing test of VLSI chips. First, the stuck-at fault testing will briefly be explained.
A fault model is a model in which a physical defect is abstracted. When the fault model is used, a fault can easily be simulated using a computer. For example, a state in which an output of a CMOS (complementary metal-oxide semiconductor) inverter keeps taking a logical value "1" can be explained by using a model in which a stuck-at 1 fault is present at the output of the inverter. As a cause of this type of fault, there can be considered a defect that a short circuit has been formed between the output of the inverter and a power supply voltage V.sub.DD or a physical defect that a drain of an nMOS (n-channel metal-oxide semiconductor) has been opened.
In the testing, a test pattern is applied to primary inputs of a circuit under test and a response pattern of the circuit appearing at primary outputs of the circuit under test is observed. A check is made, by comparing this response pattern with an expected value pattern in fault-free operation, to see whether the circuit is faulty or not. FIG. 8 shows a combinational circuit of a NAND gate ND1 having a stuck-at 0 fault and a NAND gate ND2 having no stuck-at fault. The outputs of both the NAND gates ND1 and ND2 are taken out through an OR gate OR1 as a primary output.
A test pattern which can detect the stuck-at 0 fault in this combinational circuit is "110". That is, it means that as shown in FIG. 8, the test pattern "110" is applied to the primary inputs of the combinational circuit. The reason is that when the test pattern "110" is applied to the primary inputs of the combinational circuit, the primary output of the combinational circuit is "1" in the case that the stuck-at 0 fault is not present therein, and the primary output of the combinational circuit is "0" in the case that the stuck-at 0 fault is present therein, and hence it is possible to identify whether a fault is present in the combinational circuit or not, if the test pattern "110" is applied thereto. Further, when the value of the test pattern is carefully observed, it can be seen that the test pattern is generated such that it takes an opposite or complementary logical value "1" at the site of the stuck-at 0 fault.
Recently, an integrated circuit (IC) has been miniaturized more and more, and a delay time occurring when a signal propagates on a signal path or line in an IC tends to become larger than a gate delay time. As a result, a delay fault testing has begun to be used in a microprocessor test (for example, refer to a reference literature d3). Next, a conventional delay fault testing method will briefly be explained (for example, refer to a reference literature d4).
Delay faults are classified into a gate delay fault and a path delay fault. If a delay time occurring when a signal propagates through a gate exceeds the worst value, it is said that this gate has a gate delay fault present therein. Similarly, if a delay time occurring when a signal propagates on a signal path exceeds the worst value, it is said that the signal path has a path delay fault present therein.
The delay fault testing requires two kinds of test patterns. FIG. 9 shows an example of the delay fault testing. The illustrated circuit under test is a combinational circuit configured such that it comprises a first NAND gate ND1, a second NAND gate ND2 and a third NAND gate ND3, and the outputs of the first and second NAND gates ND1 and ND2 are inputted to the third NAND gate ND3. First, an initializing pattern V.sub.1 is applied, using a slow clock, to primary inputs of the circuit under test. The initializing pattern V.sub.1 in this example is "1111". In order to prevent a delay fault from affecting the state setting, a slow clock is used. After the circuit under test has entered by transition into an expected state, a test pattern V.sub.2 is applied to the primary inputs of the circuit under test using a fast clock (high-speed clock). The test pattern V.sub.2 in this example is "0101". As a result, in FIG. 9, the upper side signal line of the two input signal lines of each of the first and the second NAND gates ND1 and ND2 (the signal line to which "0" in the V.sub.2 is inputted), and the signal lines from the outputs of the first and the second NAND gates ND1 and ND2 to the third NAND gate ND3 are activated, thereby pulses corresponding to the test pattern V.sub.2 propagate on those signal lines. Consequently, a pulse appears at the primary output of the circuit under test (the output of the third NAND gate ND3) in correspondence to its propagation delay time or transmission delay time. The value of the outputted pulse is latched using the fast clock. The latched value is used to determine whether a delay fault is present or not. Usually, a system clock is used as the fast clock. FIG. 10 shows a concept of the delay fault testing described above. A plurality of input latches 31 and a plurality of output latches 32 are connected to the preceding stage and the subsequent stage of the circuit under test (combinational circuit) 30, respectively.
It is very difficult to generate test patterns for a delay fault testing. In order to detect the target delay fault independently of its delay time and all other delay faults located in the circuit, the following condition must be satisfied. That is, both "a pulse propagating on an activated signal line" and "a pulse propagating on a branched signal line which joins the activated signal line" must be free of glitch (for example, refer to a reference literature d5). For this reason, the conventional delay fault testing method could have detected only delay faults present in limited signal lines.
As VLSI circuits are developing more and more in their density and scale, it is more difficult to synchronize all of the edges of clocks generated within a chip with the edge of the reference clock and to distribute the clock with the minimum skew. For this reason, an algorithm called H-tree configuration, for example, is introduced in the layout design of a clock-distribution network (wiring for distributing the clock). This curve called H-tree is a Hilbert curve shown in FIG. 11 (for example, refer to a reference literature d6). Since, in the H-tree, a path length ranging from the clock driver to a cell connected to each of leaf nodes is constant, the clock skew theoretically becomes zero. In addition, the Hilbert curve is self-similar and is able to reconstruct a brain structure (three-dimensional wiring layout) (for example, refer to a reference literature d7). Further, the Hilbert curve is characterized in that it can recursively draw. An application of the Hilbert curve to the clock-distribution network of three-dimensional circuit or the like is an interesting field to study.
As the operation speed or rate of a VLSI circuit is increasing more and more, at-speed testing of clock-distribution networks has become more important. However, the conventional delay fault testing method is not suitable for efficiently testing clock-distribution networks.
As shown in FIG. 12, it is difficult from the following reasons to test delay faults in a PLL circuit 40 using the aforementioned conventional delay fault testing method. First, (i) when one or more latches are added in the PLL circuit 40, an additional skew is given to the internal clock of the PLL circuit 40. As a result, an overhead is produced in order to achieve a high-speed operation to be targeted. Next, (ii) in order to latch an internal clock of the PLL circuit, a faster clock is necessary. That is, this results in a self-contradiction.